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Last updated: February 1st, 2003
(First uploaded: April 10th, 2002)

ISA data acquisition card
(Two 8-bit I/O channels)

Contents of this document
Introduction
The ISA bus
Address Decoding
Timing
Circuit Diagrams

Introduction
When working on the DTUsat project we had to do some voltage and current measurings over long periods of time (some of several days). This is, of course, not feasible to do by hand. We therefore decided to take the time and design an ISA extension card that could be used in an automatic process.

This document describes only the ISA card itself, not the additional components used for voltage, current, and temperature measuring. But for the sake of completeness I will mention that we've had great success using the MAX144 12 bit serial (SPI) A/D converters, the MAX472 bidirectional current sense amplifiers, both from Maxim, and the LM19 temperature sensor from National Semiconductors, all of which happen to be available as free samples. There is, of course, no reason not to use similar components from other vendors as well.

The ISA Bus
The ISA bus happens to be available in every PC that is a couple of years old. This is great because you can usually get 'retired' i486 or Pentium machines for free from most major companies (they all seem to be constantly upgrading their computers for the next Microsoft OS). And it doesn't matter that the PC is rather old, because we don't need a lot of speed for this project, actually a 80386 PC would be fine, but they seem to be hard to get now-a-days.

One drawback of using the ISA bus is that it tends to be removed from current PC’s and it might therefore become difficult to find a suitable computer in a couple of years. Unfortunately it isn't that easy to design a PCI or PCMCIA/PC-card solution. I'd love to have the same functionallity in a PC-card, though.

You can find some fine documents descriping the ISA bus at www.epanorama.net. The most important stuff we'll have to know is this: The layout of the bus, the fact that only the lower 11 address bits are decoded by ISA cards, and that the timing isn't standardized.

Address Decoding
Please refer to the schematic when reading this section.

The address decoding is handled by a 74138 and a 74520. The 74520 compares address bit 3 to 10 (only the lower 11 bits of the 16 bit address bus is being decoded by ISA cards) to the value programmed by wires and two jumpers. The latter allows the user to select one of 4 base addresses, namely 300h, 310h, 320h, or 330h. None of these are used in most computers. This prevents resource conflicts with other parts of the computer, and allows several cards to be used in the same computer using different addresses on each card.

The ‘138 receives the equal signal from the ‘520 and decodes the lower 3 bits into local chip select signals on the board. Two of these are combined with the io-read and io-write signals from the ISA bus and are used to generate output enable and latch enable signals for our 74574 registers. This allows the computer to read and write the registers on the board.

In order for the external components to write into the registers we need them to set the latch enable signal. Since exact timing of this kind of event might not be needed, and since it, most likely, requires additional logic on the external part I decided to use two extra chip select signals from the ‘138 to enable the external latch enable signals. Therefore you can store input values in the registers by addressing (read or write) the register address + 4:

 
read
write
base addressreads data stored in input register 1writes to output register 1
base address+1reads data stored in input register 2writes to output register 2
base address+4store external data in input register 1store external data in input register 1
base address+5store external data in input register 2store external data in input register 2

Two jumpers select whether you use internal or external latching. You need to close the jumpers for internal latching (described above), and you need to add two extra wires from U5, pin 2 to JP3 pin 18, and from U5, pin 5 to JP3 pin 24 in order to be able to use the external latching.

Timing
Normally the speed of the ISA bus is set to 8 MHz, but some systems use clock periods from anywhere between 4,77 to 16 MHz. This doesn’t really matter since ordinary 74Fxx and 74ACTxx chips are fast enough even for 16 MHz operation:

One clock cycle is 1/16 Mhz = 62,5 ns. We have 5 levels of logic, each level is thus allowed 12,5 ns, which is fulfilled by both 74Fxx and 74ATCxx chips. You can consequently choose whatever is at hand - or cheaper.

Circuit Diagrams
I used Protel 99SE with fixpack 6 to create the schematics and PCB layout. You can download a 30-days trial version (full functionality) from www.protel.com

Schematics, PCB layout etc as a zipped Protel 99SE package: isa-sch.zip (53 Kb)

I was going to upload a postscript version too, but it never turned out right, and to avoid scaling problems while printing I decided not to do it, so please use Protel if you want to print the pcb layout.

IMPORTANT
Long wires degrade the signals severely. While lengths of 50 to 75 cm (apx 2 feet) works fine wires longer than 1m (3 feet) may not work. I've tried a 1,5 m (5 feet) cable that didn't work at all due to noice induced in the cable. It is possible that this could have been fixed by using another layout of the individual wires, at least more ground wires (like in SCSI) should help. Yet I don't need the longer lengths, so I don't really care.